During semiconductor wafer fabrication, integrated circuits (ICs) that are formed on the wafer utilize layers of dielectric material, such as silicon dioxide, to provide insulation between adjacent metal segments and layers on the wafer. For example, an inter-level dielectric layer can be utilized to insulate adjacent metal layers on the wafer, while an intra-level dielectric layer can be utilized to insulate adjacent metal segments that are formed in a metal layer. However, breakdown of a dielectric layer in an IC can cause the IC to fail. Consequently, it is important for semiconductor manufacturers to conduct dielectric reliability testing during wafer fabrication. Dielectric reliability testing typically includes determining dielectric breakdown voltage, which indicates how much voltage can be applied across a dielectric layer before it breaks down.
Conventionally, dielectric breakdown voltage can be determined by utilizing a voltage ramp method, which includes applying a linearly increasing test voltage across a dielectric layer in a wafer while monitoring leakage current through the dielectric layer. The dielectric layer can be situated in, for example, a test structure formed in a dicing street on the wafer. In the conventional voltage ramp method, the test voltage is typically ramped up until an abrupt change in leakage current is detected, which indicates a breakdown of the dielectric layer. When the abrupt change in leakage current is detected, the corresponding value of the test voltage can represent the breakdown voltage of the dielectric layer.
However, in the conventional voltage ramp method, the breakdown of the dielectric layer typically results in a catastrophic failure of the dielectric layer, which causes a burn mark in the dicing street on the wafer. As a result of uncertainty as to whether the wafer has been contaminated by debris associated with the burn mark, the wafer has to be scrapped. Thus, although the conventional voltage ramp method can be utilized to determine a breakdown voltage of a dielectric layer, the catastrophic breakdown of the dielectric layer that occurs in the conventional voltage ramp method results in the wafer being scrapped, which undesirably increases manufacturing cost.